LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all; entity offset_block is generic( constant offset : integer :=2048 -- wartosc stala do dodania ); port ( input : IN STD_LOGIC_VECTOR(11 downto 0); -- 12 bitowy qwktor bitowy clk_in : IN std_logic; -- zegar output : OUT STD_LOGIC_VECTOR(11 downto 0) -- 12 bitowy qwktor bitowy ); end offset_block; architecture offset_block_arch of offset_block is signal sig : integer range 0 to 4095; -- signal ze stalym offsetem begin PROCESS(clk_in) BEGIN if rising_edge(clk_in) then sig <= to_integer(signed(input))+ offset; output <= std_logic_vector(to_unsigned(sig,12)); end if; END PROCESS; end offset_block_arch;