The website contains information and didactic materials for the subject of „Integrated electronic systems and systems” for the III year of the Electronics and Telecommunications.
During the laboratory classes, students become familiar with the basic techniques of designing the layout of integrated circuits.
- Schematic Editor
- Layout Editor (with post-layout analyses)
- Task 1 – gate – VTC optimisation
- Task 2 – gate – timing parameters optimisation
- Task 3 – complex gate
- Task 4 – D flip-flop
- Task 5 – counter
- Task 6 – buffer