
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity BlinkingLEDs_EvenOdd is
	port(
			-- Main clock and reset signal
			clk : in std_logic;
			reset_n : in std_logic := '1';
			
			leds : out std_logic_vector(7 downto 0)			
	);
end entity;


architecture BlinkingLEDs_EvenOdd of BlinkingLEDs_EvenOdd is

	constant cnt_max : unsigned(31 downto 0) := 32d"100000000";
	
	signal cnt : unsigned(31 downto 0) := (others => '0');
	signal sb : std_logic := '0';

begin


	process(clk, reset_n)
	begin
		if(reset_n = '0')then
			cnt <= (others => '0');
		elsif rising_edge(clk) then
			if(cnt < CNT_MAX)then
				cnt <= cnt + 32d"1";
			else
				cnt <= (others => '0');
			end if;
		end if;
	end process;
	
	sb <= '1' when(cnt < 32d"50000000") else '0';
	
	leds(0) <= sb;
	leds(2) <= sb;
	leds(4) <= sb;
	leds(6) <= sb;
	leds(1) <= not sb;
	leds(3) <= not sb;
	leds(5) <= not sb;
	leds(7) <= not sb;
	

end architecture;






--
--	-- ------------------------------------------------------------
--	-- Avalone Slave S0 Interface - HPS to FPGA
--	-- ------------------------------------------------------------
--	
--	process(clk, reset_n)
--	begin
--		if(reset_n = '0')then
--			avs0_readdata <= (others => '0');
--		elsif rising_edge(clk) then
--			if(avs0_write = '1')then
--				case avs0_address is
--					when AVS0_ADDR_REG0 => REG0 <= avs0_writedata;
--					when AVS0_ADDR_REG1 => REG1 <= avs0_writedata;
--					when AVS0_ADDR_REG2 => REG2 <= avs0_writedata;
--					...
--					when others => null;
--				end case;
--			elsif(avs0_read = '1')then
--				case avs0_address is
--					when AVS0_ADDR_REG0 => avs0_readdata <= REG0;
--					when AVS0_ADDR_REG1 => avs0_readdata <= REG1;
--					when AVS0_ADDR_REG2 => avs0_readdata <= REG2;
--					...
--					when others => avs0_readdata <= (others => '0');
--				end case;
--			end if;
--		end if;
--	end process;
--	