M. WIELGOSZ, G. Mazur, M. Makowski, E. JAMRO, P. RUSSEK, K. WIATR Analysis of the basic implementation aspects of hardware-accelerated density functional theory calculations Computing and Informatics 2010 vol. 29 s. 989–1000, s. 997–998
M. WIELGOSZ, E. JAMRO, K. WIATR, Hardware implementation of the exponent based computational core for an exchange-correlation potential matrix generation, Springer-Verlag, cop. 2010, Lecture Notes in Computer Science vol. 6067, S. 115–124
M. Wielgosz, E. Jamro, P. Russek, K. Wiatr, Hardware implementation of the orbital function for quantum chemistry calculations, Applied Reconfigurable Computing, ARC’2010, Springer-Verlag, LNCS 5992, s.337-342
Maciej WIELGOSZ, Ernest JAMRO, Kazimierz WIATR, Hardware implementation of the exponent based computational core for an exchange-correlation potential matrix generation, PPAM 2009 : 8th international conference on Parallel Processing & Applied Mathematics : Poland, Wrocław, September 13–16, 2009.
Jamro E., Wielgosz M., Wiatr K., Novel Reduced-Width Multiplier Structure Dedicated for FPGAs, Przegląd Elektrotechniczny (Electrical Review) R. 85 NR 8/2009, pp 66-69.
Jamro E., Cioch W., Digital signal acquisition and processing in FPGAs, Przegląd Elektrotechniczny (Electrical Review), R. 85 NR 2/2009, pp. 7-9.
Wielgosz M., Jamro E., Wiatr K., Accelerating calculations on the RASC platform. A case study of the exponential function, Applied Reconfigurable Computing, ARC’2009, Springer-Verlag, LNCS 5453, pp. 306-311.
Wielgosz M., Jamro E., Wiatr K., Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform, Computing and Informatics, Vol. 28, 2009, pp. 1001–1011
Wielgosz M., Jamro E., Wiatr K., Highly Efficient Structure of 64-Bit Exponential Function implemented In FPGAs, ARC’2008, Reconfigurable Computing: Architectures, Tools and Applications, LNCS 4943, Springer, Berlin, March 2008, pp. 274-279
Jamro E. FPGA Implementation of High Speed Diagnostic Systems, Polish Journal of Environmental Studies, vol. 16, no. 4B, 2007, pp.63-65.
Jamro E., Wielgosz M., Wiatr K., FPGA implementation of 64-bit exponential function for HPC, 17th International Conference on Field Programmable Logic and Applications, Amsterdam, Field Programmable Logic and Applications (FPL) Netherlands, 27-29 August 2007, pp. 718-721.
Batko W., Cioch W., Jamro E. Monitoring System for Grinding Machine of Turbine Engine Blades, Journal of Polish CIMAC, 2007, vol. 2 no. 2, pp. 13-18.
Jamro E. Wielgosz M. Wiatr K. FPGA Implementation of Strongly Parallel Histogram Equalisation, IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems, Kraków, Poland, April 11-13 2007, pp.93-98.
Adamczyk J., Krzyworzeka P., Cioch W., Jamro E., Monitoring of Nonstationary States in Rotating Machitery, WITE Państwowy Instytut Badawczy - Radom, Kraków 2006.
Jamro E., Wielgosz M., Wiatr K., FPGA Implementation of the Dynamic Huffman Encoder, Proc. IFAC Workshop on Programmable Devices and Embedded Systems, Brno, Feb. 14-16, 2006, pp.60-65
Jamro E., Wiatr K. A Novel Parallel-Serial Architecture for Neural Networks Implemented in FPGAs, Proc. of IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop, Sopron, 13-16 Apr. 2005, pp.121-128.
Jamro E. Waitr K. Heterogeneous Hardware-Software Prototyping System for PC-controlled FPGA-based Designs, Proc. of IFAC Workshop on Programmable Devices and Systems PDS, Cracow, Nov. 18-19 2004, pp. 186-191
Jamro E., Wiatr K.: Constant Coefficient Convolution Implemented in FPGAs, Proc. of the Euromicro Symposiumon Digital System Design, Dortmund 2002, IEEE CS Press, Los Alamitos 2002, pp. 291-298
Jamro E., Wiatr K.: Dynamic Constant Coefficient Convolvers Implemented in FPGA, Lecture Notes in Computer Science, Proc. of the 12th International Conference on Field Programmable Logic and Applications, Berlin, Springer 2002, pp. 1110-1113
Jamro E. Parameterised automated generation of convolvers implemented in FPGAs, Ph.D. Thesis, University of Mining and Metallurgy (AGH), Kraków, Poland, June 2001.
Wiatr K. Jamro E. Implementation of convolution operation on general purpose processors Proceedings of the Euromicro Conf. on Multimedia and Telecommunication 2001, IEEE Computer Society.
Jamro E., Wiatr K., Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution, Proc. of the IEEE Int. Conf. Digital System Design, Warszawa, Poland, 4-6 Sep. 2001, pp. 466-473, IEEE Computer Society.
Jamro E., Wiatr K. FPGA implementation of addition as a part of the convolution, IEEE Euromicro Conference, Warszawa Poland, 4-6 Sep. 2001, IEEE Computer Society.
Jamro E., Wiatr K., Implementation of real time image convolution in FPGA structures, Image Processing & Communications, An International Journal, Bydgoszcz 2001, pp. 55-63.
Jamro E., Wiatr K., Convolution Operation Implemented in FPGA Structures for Real Time Image Processing, Proc. of the IEEE Int. Symposium on Image Processing and Analysis, Pula, Croatia, 19-21 June 2001.
Wiatr K. Jamro E. Układy mnożące przez stały współczynnik implementowane w układach programowalnych FPGA, Kwartalnik Elektronika i Telekomunikacja PAN, Warszawa 2001, Tom 47, Zeszyt 2, pp. 231-251.
Wiatr K. Jamro E. Implementation of Multipliers in FPGA Structures, IEEE International Symposium on Quality Electronic Design, San Jose, California 26-28 March 2001, pp. 415-420, IEEE Computer Society.
Wiatr K. Jamro E. Implementacja arytmetyki rozproszonej w układach programowalnych FPGA na przykładzie operacji konwolucji 2D, Kwartalnik Elektronika i Telekomunikacja AGH, Tom 19, Zeszyt 2, Kraków 2000, s. 98-104
Wiatr K. Jamro E. Implementacja algorytmu konwolucji 2D w procesorach ogólnego przeznaczenia i w układach specjalizowanych VLSI. Kwartalnik Elektronika i Telekomunikacja PAN, Tom 46, Zeszyt 4, 2000, s 553-587.
Jamro E. Automatyczna synteza układów z parametrem w języku VHDL na przykładzie kodeka kodu BCH, Krajowe Sympozjum Telekomunikacji? 2000, 6-8 wrzesień 2000, ATR Bydgoszcz. Vol D. p. 59-64.
Wiatr K., Jamro E. Constant Coefficient Multiplication in FPGA Structures, IEEE Proceedings of the 26th Euriomicro Conference, Maastricht, The Netherlands, Sep. 5-7, 2000, Vol. I, pp. 252-259, IEEE Computer Society.
Wiatr K. Jamro E. Implementation of image data convolutions operations in FPGA reconfigurable structures for real-time vision systems. International IEEE Conference on Information Technology: Coding and Computing, Nevada 2000, pp. 152-157
Wiatr K. Jamro E. Implementacja algorytmu konwolucji 2D dla potrzeb przetwarzania obrazów w czasie rzeczywistym. Kwartalnik Elektrotechnika i Elektronika, Tom 18, Zeszyt 4, 1999, pp. 157-169.
Wiatr K. Jamro E. Obliczanie algorytmu konwolucji dla potrzeb przetwarzania obrazów w czasie rzeczywistym, II Krajowa Konferencja Metody i systemy komputerowe w badaniach naukowych i projektowaniu inżynierskim, Kraków 25-17 X 1999, pp. 459-464.
Jamro E. Synteza układów z parametrem w języku VHDL na przykładzie kodeka kodu BCH. II Krajowa Konferencja Metody i systemy komputerowe w badaniach naukowych i projektowaniu inżynierskim, Kraków 25-17 X 1999, pp. 39-43.
Jamro E, Fenn STJ, Taylor D, Benaissa M. Hardware-efficient multiplication in Berlekamp-Massey algorithm circuits. Proceedings of First International Symposium on Communication Systems and Digital Signal Processing, 1998. Sheffield Hallam Univ. Press. Part vol.1, 1998, pp.60-3 vol.1. Sheffield, UK.
Jamro E. The design of a VHDL synthesis tool of BCH codes, Master of Philosophy Thesis, University of Huddersfield U.K. September 1997.
Research interests: